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Categories | Programmable IC Chip |
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Brand Name: | INTEL/ALTERA |
Model Number: | EP2C8Q208C8N |
Place of Origin: | original |
MOQ: | 1 |
Price: | Negotiable |
Payment Terms: | L/C, D/A, D/P, T/T, Western Union, MoneyGram |
Supply Ability: | 999999 |
Delivery Time: | 1-3 days |
Packaging Details: | standard |
Total RAM Bits: | 165888 |
Voltage - Supply: | 1.15V ~ 1.25V |
Mounting Type: | Surface Mount |
Operating Temperature: | 0°C ~ 85°C (TJ) |
Package / Case: | 208-BFQFP |
Supplier Device Package: | 208-PQFP (28x28) |
pn: | EP2C8Q208C8N |
EP2C8Q208C8N Programmable IC Chip
Field Programmable Gate Array (FPGA) IC 138 165888 8256 Package
208-BFQFP
Number of LABs/CLBs | 516 | |
Number of Logic Elements/Cells | 8256 | |
Total RAM Bits | 165888 | |
Number of I/O | 138 | |
Voltage - Supply | 1.15V ~ 1.25V | |
Mounting Type | ||
Operating Temperature | 0°C ~ 85°C (TJ) | |
Package / Case | ||
Supplier Device Package | 208-PQFP (28x28) |
EP2C8Q208C8N Features
The Cyclone II device family offers the following features:
■ High-density architecture with 4,608 to 68,416 LEs
● M4K embedded memory blocks
● Up to 1.1 Mbits of RAM available without reducing available logic
● 4,096 memory bits per block (4,608 bits per block including 512
parity bits)
● Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18,
×32, and ×36
● True dual-port (one read and one write, two reads, or two writes)
operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes
● Byte enables for data input masking during writes
● Up to 260-MHz operation
■ Embedded multipliers
● Up to 150 18- × 18-bit multipliers are each configurable as two
independent 9- × 9-bit multipliers with up to 250-MHz performance
● Optional input and output registers
■ Advanced I/O support
● High-speed differential I/O standard support, including LVDS,
RSDS, mini-LVDS, LVPECL, differential HSTL, and differential SSTL
● Single-ended I/O standard support, including 2.5-V and 1.8-V,
SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI
and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-,
and 1.8-V LVTTL
● Peripheral Component Interconnect Special Interest Group (PCI
SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V
operation at 33 or 66 MHz for 32- or 64-bit interfaces
● PCI Express with an external TI PHY and an Altera PCI Express
×1 Megacore® function
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