200MHz Real Time USRP Software Defined Radio Ettus N321 Fault Tolerance

Software Defined Radio,USRP-LW N321, Compatible with ETTUS USRP N321

Product Overview

The USRP-LW N321 is a networked software defined radio that provides reliability and fault-tolerance for deployment in large scale and distributed wireless systems. This is a high performance SDR that uses a unique RF to provide 2 RX and 2 TX channels. Each channel provides up to 200 MHz of instantaneous bandwidth and covers an extended frequency range from 3 MHz to 6 GHz. The baseband processor uses the Xilinx Zynq-7100 SoC to deliver a large user programmable FPGA for real-time, low latency processing and a dual-core ARM CPU for stand-alone operation. Support for 1 GbE, 10 GbE, and Aurora interfaces over two SFP+ ports and 1 QSFP+ port enables high throughput IQ streaming to a host PC or FPGA coprocessor.

A flexible synchronization architecture with support for 10 MHz clock reference, PPS time reference, external TX and RX LO input, and GPSDO enables implementation of phase coherent MIMO testbeds. With the ability to import both TX and RX LOs for any supported frequency above 450 MHz, the USRP N321 provides a path to building large, phase coherent MIMO testbeds for a variety of advanced wireless research topics. In addition, the USRP N321 allows for the export of TX and RX LOs in a Star configuration to multiple other USRP N320 or USRP N321 devices.

The USRP N321 leverages recent software developments in UHD to simplify control and management of multiple devices over the network with the unique capability to remotely administrate tasks such as debugging, updating software, rebooting, resetting to factory state, and monitoring system health.

Main Features

• Reliable and fault-tolerant deployment
• Remote management capability
• Stand-alone (embedded) or host-based (network streaming) operation
• Fully integrated and assembled (the USRP N321 does not support swappable daughtercards)
• 3 MHz to 6 GHz extended frequency range
• Up to 200 MHz of instantaneous bandwidth per channel
• 2 RX, 2TX in half-wide RU form factor
• RX, TX filter bank
• 14 bit ADC, 16 bit DAC
• Master clock rates: 200, 245.76, and 250 MS/s
• Xilinx Zynq-7100 SoC
  • Dual-core ARM Cortex-A9 800 MHz CPU
• One QSFP+ port
• Two SFP+ ports (1 Gigabit Ethernet, 10 Gigabit Ethernet, Aurora
• RJ45 (1 GbE)
• Clock reference
• PPS time reference
• External RX, TX LO input ports
• White Rabbit
• Built-in GPSDO
• 1 Type A USB host port
• 1 micro-USB port (serial console, JTAG)
• Trusted Platform Module v1.2
• Watchdog timer

Technical index:

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